1. Field of the Invention
This invention relates to an architecture, circuitry and method for avoiding a non-desired output from a latch. The latch is operable from set and reset inputs, and is programmed to prohibit the latch output entering into a state or condition where complementary output signals from the latch are at the same logic level.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
A latch is typically understood to be any device which can store information. A popular form of a latch is alternatively known as a xe2x80x9cflip-flop.xe2x80x9d A latch or flip-flop is designed to produce an output that is stable in one of two logic states. The output logic level will remain until the input to the latch undergoes a change in logic level.
Output from the latch can be at a xe2x80x9ctrue,xe2x80x9d xe2x80x9con,xe2x80x9d xe2x80x9chigh,xe2x80x9d or xe2x80x9c1xe2x80x9d logic level or, alternatively, at a xe2x80x9cfalse,xe2x80x9d xe2x80x9coff,xe2x80x9d xe2x80x9clow,xe2x80x9d or xe2x80x9c0xe2x80x9d logic level. For convenience in relating relativity to logic level, the former logic level, logical 1, is assumed to be the most positive voltage and the latter logic level, logical 0, represents the most negative voltage value. This relationship is known as positive logic and is used as a convention herein.
There are several types of latches used to store logical 1 or logical 0 logic levels. Latches can be classified as either clocked or non-clocked. If clocked, a clock pulse controls the times at which outputs from the latch can transition. For example, a toggle latch will impart toggling action on the output of the latch during transitions of the clock pulse whenever the toggling input is at a logical 1 logic level. Other forms of latches may not require any clock input whatsoever. For example, a set/reset (SR) latch causes an output from the latch to be set or reset dependent on the logic levels of signals placed on the set and reset inputs.
Regardless of whether a latch is clocked or not, there are generally two complimentary outputs produced from a latch. The complimentary outputs are oftentimes referred to as differential outputs, in that while one output is at a logical 1 logic level, the other output is at a logical 0 logic level (i.e., complimentary of the former logic level). The complimentary outputs are oftentimes labeled Q and Qxe2x80x2. When one output is at the logical 1 state, the other output is always at a logical 0 state. If the latch changes state, then both Q and Qxe2x80x2 change. A latch is considered to be xe2x80x9csetxe2x80x9d when Q is in a logical 1 state and Qxe2x80x2 is in a logical 0 state. Conversely, the latch is xe2x80x9cresetxe2x80x9d when Q is in a logical 0 state, and Qxe2x80x2 is in a logical 1 state. Generally, a latch is reset in anticipation of it being subsequently set to store binary information.
A simple example of a non-clocked set/reset (SR) latch is shown in FIG. 1. In particular, FIG. 1 illustrates a NAND gate SR latch 10a and a NOR gate SR latch 10b. Latch 10a comprises a pair of cross-connected NAND gates 12 and 14, while latch 10b comprises a pair of cross-connected NOR gates 16 and 18. Latches 10 have two inputs labeled S and R (for set and reset) and, therefore, are classified as SR latches. Each latch 10 also has a pair of complimentary outputs labeled Q and xe2x80x9cQ barxe2x80x9d (or Qxe2x80x2).
Referring to the truth tables 20a and 20b, logic levels are shown for outputs Q and Qxe2x80x2 corresponding to inputs S and R. Truth table 20a represents the operation of the NAND gate SR latch 10a, while truth table 20b represents the operation of the NOR gate SR latch 10b. Referring to truth table 20a, it can be seen that if the S input goes to a logic 0 level, then the latch will go to its set state (Q equals a logic 1 level), and will remain in that state until reset. When the R input goes to a logic 0 level, then the latch will go to its reset state and stay there until it is set again. Thus, an SR latch changes state upon sensing a change in state at the S or R inputs, and stores the results of the change until the opposite input is activated. Truth table 20b indicates that the NOR gate SR latch will go to a set state whenever the S input goes to a logic 1 level, and will go to a reset state when the R input goes to a logic 1 level.
The set and reset states are noted as xe2x80x9cSETxe2x80x9d and xe2x80x9cRSTxe2x80x9d shown in FIG. 1. In addition to the set and reset states, there are two special conditions of interest for an SR latch. First, whenever the S and R inputs are at a logic 1 level (for the NAND gate embodiment 10a) or at a logic 0 level (for the NOR gate embodiment 10b) no change is made to the complimentary outputs. This state is noted as a memory (xe2x80x9cMEMxe2x80x9d) state since the outputs retain their previous logic levels. However, if the set and reset inputs are at a logic 0 level (for the NAND gate embodiment 10a) or at a logic 1 level (for the NOR gate embodiment 10b), then the complimentary output conductors enter the same state: either logic 1 level for the NAND gate latch 10a or a logic 0 level for the NOR gate latch 10b. Having the same logic level on the complimentary output is not desired and, accordingly, this state is labeled xe2x80x9cND.xe2x80x9d
A non-desired output state is to be prevented for at least two reasons. First, the complimentary outputs are generally used elsewhere in the circuit subsystem. That subsystem depends on the Q output being 180xc2x0 out of phase with the Qxe2x80x2 output. Having the Q and Qxe2x80x2 outputs at the same logic levels could be catastrophic to the operation of any load coupled to receive complimentary inputs. Second, the non-desired state can produce non-deterministic logic levels. For example, if a transistor within logic gate 14 is made having stronger drive outputs than a transistor within NAND gate 12, then even through the set and reset inputs are at a logic 0 level, the Q output may skew to a differential logic level from that of the Qxe2x80x2 output. This may indicate a set state when, in fact, the set and reset inputs are not in a set condition (e.g., the set input being at a logic 0 level and the reset input being at a logic 1 level for the exemplary NAND gate example).
Most designers attempt to avoid placing a latch in a non-desired state. However, there may be times when the non-desired state is difficult to avoid and is uncontrollably dependent on the set and reset input conditions. It would therefore be desirable to introduce an improved SR latch that, regardless of the SR input values, the latch can never enter a non-desired state. The improved latch would represent a considerable advance over conventional SR latches since a designer can use such a latch with impunity, and with little regard to controlling the set and reset inputs for the purpose of avoiding the non-desired state.
The problems outlined above are in large part solved by an improved latch. Preferably, the latch is an SR latch that need not be clocked, and can avoid non-desired states. The latch can be implemented as a quasi-NAND gate or quasi-NOR gate configuration. In addition to the set and reset inputs, the latch also receives programmable inputs. Depending on the logic value of the programmable inputs, the latch can be programmed to give priority to the set input, the reset input, or both.
The programmed inputs are fed onto gate conductors or base conductors of respective transistors coupled in series with the transistors, which receive the set and reset inputs. The series-connected resistors are cross-coupled with and parallel to corresponding transistors within a memory or latch cell. The pairs of series-connected transistors can, therefore, form a prioritizer or priority encoder according to one embodiment. The memory element simply stores complimentary outputs produced from the prioritizer and retains those outputs onto the output conductors. A selector can be used to select either xe2x80x9cset barxe2x80x9d (setxe2x80x2), xe2x80x9creset barxe2x80x9d (resetxe2x80x2), or both setxe2x80x2 and resetxe2x80x2 to be placed on the programmable inputs of the prioritizer.
The latch can be implemented using solely n-type (NMOS) transistors or bipolar (NPN) transistors. Alternatively, the latch can use p-type (PMOS) transistors or PNP transistors. If implemented with the latter form of transistors, then the set and reset inputs can receive complimentary set and reset values, while the programmable inputs can receive set, reset, or set and reset values. Use of, for example, PMOS transistors rather than NMOS transistors merely indicate that the values on the set, reset, and programmable inputs are switched to the corresponding complimentary values. This also applies to switching between either a sourcing power supply or ground. If NMOS transistors are used, then a sourcing power supply (VDD) is used on one programmable input and if PMOS transistors are used, then a ground (VSS) is used in lieu of VDD.
According to one embodiment, a latch includes a pair of output conductors, a set conductor, and a reset conductor. The latch further includes a circuit coupled to retain dissimilar logic values upon the pair of output conductors whenever the same logic value is placed on the set and reset conductors. In other words, the latch will avoid the non-desired state.
According to another embodiment, a circuit such as a latch can include a selector and a prioritizer. The selector chooses among a set of voltage values, and the prioritizer receives set and reset input signals of the same logic value and will match dissimilar logic values upon output signals depending on which voltage value is selected by the selector. The prioritizer can, therefore, establish the set input value priority over the reset input value priority, or vice-versa, depending on which voltage value is chosen by the selector.
According to yet another embodiment, a method is provided for preventing a non-desired output from a latch. The method includes receiving a similar logic value upon set and reset conductors of the latch, while preventing the latch from producing a similar logic value on differential output conductors of the latch.